Low profile multi-IC chip package connector

ABSTRACT

A low profile multi-IC chip package for high-speed applications comprises a connector for electrically connecting the equivalent outer leads of a set of stacked primary semiconductor packages. In one embodiment, the connector comprises a two-part sheet of flexible insulative polymer with buses formed on one side. In another embodiment, the connector comprises multiple buses formed from conductive polymer. In further embodiments, the primary packages are stacked within a cage and have their outer leads in unattached contact with buses within the cage or, alternatively, are directly fixed to leads or pads on the host circuit board.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of application Ser. No. 10/792,222,filed Mar. 3, 2004, pending, which is a continuation of application Ser.No. 10/200,792, filed Jul. 22, 2002, now U.S. Pat. No. 6,773,955, issuedAug. 10, 2004, which is a continuation of application Ser. No.09/792,771, filed Feb. 23, 2001, now U.S. Pat. No. 6,475,831, issuedNov. 5, 2002, which is a continuation of application Ser. No.09/349,522, filed Jul. 8, 1999, now U.S. Pat. No. 6,258,623, issued Jul.10, 2001, which is a continuation of application Ser. No. 09/138,372,filed Aug. 21, 1998, now U.S. Pat. No. 6,153,929, issued Nov. 28, 2000.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates generally to semiconductor device assemblieshaving molded housings. More particularly, the invention relates toconnectors for joining a stack of packaged devices into a small multi-ICchip assembly package operable at high speeds.

2. Description of the Related Art

The evolution of the computer has resulted in a requirement for greatlyincreased memory capacity in much smaller packages. Another requirementis the capability for reliable operation at much higher clock speeds,e.g. up to 800 MHZ or more. In addition, the memory device(s) must bereadily produced in high quantity and at low cost with reduced rates offailure or rejection. One way to provide a greater memory storagecapacity in a smaller space is by stacking a plurality of memory chipsand interconnecting them to produce a limited number of connections toe.g., a circuit board. In so doing, a number of factors must beaddressed, including heat dissipation, ease of interconnection,impedance effects, etc.

Combining two or more semiconductor dice or chips in a singlesemiconductor device assembly has been used to reduce the space requiredfor integrated circuits. Such devices are generally known as multi-chipmodules (MCM). In one form, dice are stacked vertically on oppositesides of a substrate, for example, or atop each other with interveninginsulative layers, prior to encapsulation. Examples of such devices areshown in U.S. Pat. No. 5,239,198 to Lin et al., U.S. Pat. No. 5,323,060to Fogal et al. and U.S. Pat. No. 5,495,398 to Takiar et al.

U.S. Pat. No. 5,604,377 discloses a rack with multiple shelves forholding unpackaged chips. The chips are electrically connected by leadframes to a wiring interface on a vertical circuit board which can beconnected to a PCB. The entire assembly is contained in a sealedenclosure.

In U.S. Pat. No. 5,602,420 to Ogata et al., multiple unpackaged dicehaving peripheral bond pads are spacedly stacked, and corresponding bondpads are soldered with meltable balls to one of a plurality of metalleads perpendicular to the dice. The active surfaces of the dice may becoated with an insulative layer after lead bonding, and/or the entiremulti-die device may be encapsulated.

U.S. Pat. No. 5,637,912 discloses a multi-chip module in which chips arestacked in a vertical arrangement, and a metallization pattern isdeposited on a surface formed by the chip edges.

MCM devices are also made which combine a number of dice side-by-side ona substrate. The conventional single in-line multi-chip module (SIMM)and dual in-line multi-chip modules (DIMM) are common examples of thisMCM configuration. Other examples are shown in U.S. Pat. No. 5,137,836to Lam, U.S. Pat. Nos. 4,992,849 and 4,992,850 to Corbett et al., U.S.Pat. No. 5,255,156 to Chang, U.S. Pat. Nos. 5,239,747 and 5,461,544 toEwers, U.S. Pat. No. 5,465,470 to Vongfuangfoo et al., and U.S. Pat. No.5,480,840 to Barnes et al.

U.S. Pat. No. 5,592,019 to Ueda et al. shows multiple single-chippackages connected on end to a substrate by their leads.

The y-axis stacking of multiple packaged devices has been used in aneffort toward miniaturization. In U.S. Pat. No. 5,155,067, a multi-chippackage is shown wherein packaged devices are stacked in a housing andsealed with a covering lid. The outer leads of the devices are connectedby, e.g., solder to conductive pads on the housing, and the pads areattached to, e.g., DIP style leads for attachment to a circuit board.

A stackable carrier for chips is shown in U.S. Pat. No. 4,996,587 toHinrichsmeyer et al. A single chip or die is adhesively positioned in anunderside recess in the carrier and conductive wires from the die arepassed through a hole and bonded to conductors formed on the uppersurface of the carrier. S-shaped connector clips are soldered to each ofthe I/O leads on opposed edges of the carrier and to the clips of othercarriers stacked with it to form a multi-chip package (MCM).

In U.S. Pat. No. 5,514,907 to Moshayedi, a multi-chip memory module hasa plurality of stacked IC devices between opposing “side boards,” thelatter comprising circuit boards with a pattern of interconnected viasinto which the pins of the devices are soldered. The pins of thelowermost device are also soldered to the substrate, such as a maincircuit board, and comprise the interconnection between the module andthe circuit board.

U.S. Pat. No. 5,420,751 to Bums discloses a stacked IC package which hasvertical metal rails which pass through a cap above the packageddevices. Each rail is soldered to corresponding outer leads of theprimary packages and has a lower end connectable to a PCB. The primarydevices are adhesively joined to prevent movement of the devices in thestack package. Manufacture of the rails is a complex process, and themanipulation of a large number of parts to form the multi-IC chippackage may be counterproductive.

In a later issued patent to Burns, U.S. Pat. No. 5,484,959, a stackpackage for thin small outline package (TSOP) devices is shown withvertical metal rails for each set of corresponding outer leads of theTSOP devices. A secondary “lead frame” for each TSOP package hassecondary leads which are soldered to the pins of the TSOP package andto the metal rails. Each secondary lead is particularly formed with a“flex offset” to provide a stress relief connection with the rail.

As disclosed, the Bums apparatus requires a second lead frame for eachpackaged primary device. Furthermore, additional steps are required toform the stress relief offset. Furthermore, maintaining the rails inparallel non-contact alignment during and following soldering appears tobe a major problem. A large number of soldering steps is required tojoin the large number of parts.

The aforementioned prior art patents disclose multi-chip apparatuseswhich are deficient in one or more of the following (or other) aspects:

-   -   a. The multi-chip module is complex to make, using a large        number of parts which must be formed, aligned and individually        secured in the device.    -   b. The y-dimension (perpendicular to the host PCB) of the        multi-chip module is relatively great, and may be excessive for        the particular end use.    -   c. Removal and replacement of a flawed primary device in the        module is extremely difficult and may exceed the value of the        module.    -   d. The inability to pre-test each primary device prior to        incorporation into the multi-chip module results in an increased        failure rate in the final multi-chip device.    -   e. The leads and connections result in excessive impedance        effects at high clock speeds, i.e. greater than about 400 MHZ,        and particularly at speeds now anticipated, i.e. about 800 MHZ        and higher.

Among the many considerations in constructing semiconductor devices isthermal expansion. With multi-chip devices in particular, elasticity isrequired in the electrical connections to accommodate thermal expansion,as well as dimensional variation in the primary devices.

U.S. Pat. No. 5,600,183 to Gates, Jr. discloses a conductive adhesivecomprising a mixture of, e.g., silver powder in an epoxy material.

U.S. Pat. No. 5,468,655 to Greer discloses a temporary electricalconnection comprising a metal paste applied to contact pads, then heatedto partially melt the metal. A solder bump may then be placed in contactwith the metal paste and heated to join the bump thereto.

BRIEF SUMMARY OF THE INVENTION

The present invention comprises a stack package connector by which astack of primary packaged semiconductor devices is joined to provide asecondary package which is joinable to a printed circuit board or otherhost apparatus. In the invention, equivalent outer leads of the primarypackages are joined by flexible conductive buses having low impedanceand induction effects. One end of each bus is directly connectable tocontact pads or other contact means of a host printed circuit board(PCB) or other electronic apparatus.

In one aspect of the present invention, a plurality of encapsulatedintegrated circuit packages is adhesively joined to provide a stack toprovide one or more planes in which corresponding outer leads arepositioned in vertical alignment. The outer leads of each IC package arecut close to the package bodies. Conductive buses are formed to joincorresponding outer leads of the packages and terminate in bus endsjoinable to e.g. a PCB (printed circuit board).

In one form of conductive bus, an elongate Y-axis conductor tape isformed of a non-conducting material having parallel linear conductiveelements, i.e. buses, formed to span the tape. On one side of the tape,the conductor ends are configured to enable ready connection to buslines of a circuit board. The width of the tape may be varied toaccommodate different numbers of stacked packages of differingthicknesses in the stack package. The buses of the tape are joined tothe exposed outer leads of the primary packaged devices, typically in asingle step utilizing pressure, conductive adhesive and/or other method.The polymer portion of the tape between the buses may further have anadhesive surface for adhesion to the stacked devices.

In another form of conductive bus, the stack is placed on a circuitboard with conductive pads and a thin stream of conductive adhesivematerial such as a metal containing epoxy is applied to correspondingouter leads and a conductive pad to form a conductive bus.

In another aspect of the invention, a hollow cage is formed forcontaining the stacked packaged devices. In one embodiment of theinvention, a pattern of bus traces is formed on a “flex PCB” andattached to one inner wall of the cage. Each bus trace terminates in atab or lead end which is attachable to a host circuit board. The outerleads of packages stacked in the cage are bent to provide a degree offlexibility, and the flex PCB may be attached to the cage wall with anelastomeric adhesive to provide additional resiliency for accommodatingvariations in package dimensions. The packages are stacked in the cagewith friction fit, i.e. without being adhesively joined to each otherand having the outer leads simply contacting the bus traces withoutbeing joined to them by solder or other joining means. Thus, the primarypackaged devices may be individually removed and replaced withoutdesoldering or other disjoining step.

In a further embodiment of the present invention, the cage is formedsuch that the primary packages have their major planar surfaces alignedat right angles to the surface of the host PCB. The single plane ofouter leads is placed against and joined to conductive pads on thesurface of the host PCB. Thus, each outer lead may be joined to aconductive pad. In an alternate version, the PCB is formed with a seriesof elongate conductive pads. The equivalent outer leads of all primarypackages may be joined as a set to a single elongate pad of the PCB.

In this description, the terms “chip” and “die” are usedinterchangeably. In addition, the term “primary packaged device” refersto an encapsulated package containing one or more dice, each typicallyconnected to a conductive lead frame having outer leads or pins. Suchpackaged devices are typically identified as small outline J-lead (SOJ),thin small outline packages (TSOP), plastic leaded chip carrier (PLCC),single in-line plastic (SIP), dual in-line plastic (DIP), and otherdescriptive names. The term “secondary packaged device” refers to adevice formed by combining a plurality of primary packaged devices in asingle module and interconnecting the primary devices to provide asingle set of electrodes connectable to a circuit board or other hostelectrical apparatus.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The invention is illustrated in the following figures, wherein theelements are not necessarily shown to scale and certain features may beexaggerated in dimension:

FIG. 1 is a perspective view of a low profile multi-IC chip packageincorporating a package connector of the invention;

FIG. 2 is a cross-sectional view of a package connector for a lowprofile multi-IC chip package of the invention, as taken along line 2-2of FIG. 8;

FIG. 3 is a cross-sectional view of another embodiment of a packageconnector for a low profile multi-IC chip package of the invention, astaken along line 2-2 of FIG. 8;

FIG. 4 is a cross-sectional view of a further embodiment of a packageconnector for a low profile multi-IC chip package of the invention, astaken along line 2-2 of FIG. 8;

FIG. 5 is a cross-sectional view of an additional embodiment of apackage connector for a low profile multi-IC chip package of theinvention, as taken along line 2-2 of FIG. 8;

FIG. 6 is a cross-sectional view of another embodiment of a packageconnector for a low profile multi-IC chip package of the invention, astaken along line 2-2 of FIG. 8;

FIG. 7 is a side view of a Y-axis conductive tape of a package connectorof the invention;

FIG. 8 is a top view of a Y-axis conductive tape of a package connectorof the invention;

FIG. 9 is a perspective view of another embodiment of a low profilemulti-IC chip package incorporating a package connector of theinvention;

FIG. 10 is a partial end view of a low profile multi-IC chip packageillustrating the formation of an electrical bus of a connector thereof;

FIG. 11 is a plan view of a further embodiment of a low profile multi-ICchip package incorporating a package connector of the invention;

FIG. 12 is a cross-sectional side view of an embodiment of a low profilemulti-IC chip package incorporating a package connector of theinvention, as taken along line 11-11 of FIG. 11; and

FIG. 13 is a cross-sectional side view of another embodiment of a lowprofile multi-IC chip package incorporating a package connector of theinvention.

DETAILED DESCRIPTION OF THE INVENTION

An improved low profile, high-speed multi-IC chip connector andresulting stack package for memory chips is provided by the presentinvention. Different embodiments of the connector are illustrated in thedrawing figures. The connector is joined to a stack of encapsulatedsemiconductor devices, each of which comprises a primary packagecontaining one or more electrically connected dice. Preferably, eachpackage has been burned-in and tested prior to joining to the connectoras part of a stack. The stack package typically comprises at least twoprimary packages, although the number of packages is more normally about4 to 8, or more. Any number of primary packages may be incorporated in asecondary package, limited only by such considerations as spacerequirements, the effect of bus length upon impedance, and the like.Additionally, the secondary package is suitable for use of primarypackages having clock speeds of at least 400 MHZ, 800 MHZ, or greater.

The various embodiments of the invention are particularly applicable tohigh-speed memory packages such as are required to achieve processingspeeds of 800 MHZ or higher.

The speed capability of prior art memory chips has lagged the capabilityof RAM (random access memory) chips, and has been a significant limitingfactor in the production of high-speed computers and the like foroperation at clock speeds of 600 MHZ and higher. This invention may beparticularly applied to the advancement of memory chips, replacingcurrent SIMM and DIMM module designs which are inadequate.

Turning now to drawing FIG. 1, one embodiment of a multi-chip package 10of the invention is illustrated. The multi-chip package 10 is shown witha stack 12 of four primary semiconductor packaged devices 14, alsosimply called “primary packages” herein, such as are well known in theart. Each primary package 14 contains at least one semiconductor diehaving interconnections such as by a lead frame to a plurality of outerleads 16. The semiconductor die and lead frame are not visible in thedrawing figures, being within the protective layer of, e.g., insulativepolymer on the exterior of each primary package 14. Each primary package14 is shown with major upper and lower surfaces 18 and 20 which areconnected by ends 22, 24 and lateral edges 26 and 28. Truncated outerleads 16 are shown extending outwardly from each of lateral edges 26 and28, respectively. The primary packages 14 are joined to each other andto a host circuit board 30 by nonconductive adhesive material 32, whichmay be a tape such as Kapton polyimide, or a flowable adhesive cement.Circuit board 30 is shown with electrically conductive pads 34 forconnection to the multi-chip package 10.

The primary packages 14 are electrically joined by a flexible connector36, details of which are shown in drawing FIGS. 1-8.

The connector 36 comprises a layer 38 of insulative polymeric materialsuch as Kapton polyimide. On one side 42 of the polymeric layer 38 issuperposed a series of parallel conductive buses 40. The buses 40 arespaced on the polymeric layer 38 to match the spacing of the outer leads16. The buses 40 may be metal wire of varied cross-sectional shapes andadhesively joined to the polymeric layer 38.

Shown in drawing FIGS. 2-6 are five exemplary configurations of bus 40which may be used in the connector 36. Other shapes may also be used.The bus may be a simple round wire 40A attached with adhesive 44 to side42 of the polymeric layer 38, as shown in FIG. 2. The pitch 48 of thewires 40A is controlled to equal the spacing or pitch of the outer leads16. Side 54 of the polymeric layer 38 is the external surface of theconnector 36.

In drawing FIG. 3, a semi-round wire 40B is depicted, and drawing FIG. 4shows a flat wire 40C attached with adhesive 44. As depicted in drawingFIG. 5, a flat wire 40D with side grooves 46 for enhancing theattachment forces of the wire to the polymeric layer 38 with adhesive 44is shown.

Where the polymeric layer 38 is a thermoplastic, the bus 40 may beattached to the polymeric layer 38 by heating the wire and pressing itinto the polymeric layer. As shown in drawing FIG. 6, the wire 40E mayhave a shape which includes a lock 50 which is embedded in the polymericlayer 38 for firmly attaching the bus to the polymeric layer. The wire40E may be heated by passing an electric current through the wire.

As depicted in drawing FIG. 1, the flexibility of the connector 36permits conformation to the rows of outer leads 16 and the lateral edges26, 28 of the primary packages 14. The bending of the connector 36 isexaggerated in FIG. 1 for better comprehension. Use of the connector 36of drawing FIG. 1 permits formation of a four-package multi-chip packagedevice 10 having an overall height 64 (FIG. 12) of about 6 mm or less.

The polymeric layer 38 of the connector 36 may have a typical thickness52 (FIG. 2) of about one (1) to about five (5) mils, and is preferablyformed of polyimide, although other suitable polymers may be used. Thebuses 40 have cross-sectional dimensions such that the impedance andinductance are sufficiently low to enable high quality operation at thespecified clock speed and power rating. For example, in a multi-chipdevice of four primary memory packages, a suitable round aluminum wire40A provides acceptable conductance and impedance.

In a preferred embodiment, the outer leads 16 of the primary packages14, as well as the buses 40, have a uniform pitch, i.e. spacing.

As shown in drawing FIG. 1, the buses 40 of connector 36 are attached tothe outer leads 16 of the primary packages 14 such that the equivalentouter leads of the packages are attached to the same bus. Each bus 40has one end 56 which is attachable to a conductive pad 34 of the hostcircuit board 30. The bus-to-lead and bus-to-pad connections may be madewith heat, e.g. a low temperature solder, by pressure, or withapplication of a conductive adhesive, or by any suitable well knownconnection methods in the art.

As depicted in drawing FIGS. 7 and 8, the connector 36 may be formed asa semicontinuous tape 58 with transverse buses 40 attached to thepolymeric layer 38, e.g., Kapton™ polyimide. The tape 58 may bepre-manufactured to provide the desired bus configurations, pitch 48 andtape widths 60 applicable to a manufacturer's product line. The tape 58is cut to fit each multi-IC chip package. As shown, the tape may beplaced on a spool 62 for easy dispensing and use. Alternately, aflex-circuit having transverse buses 40 secured to an etched polymericlayer 38 exposing the buses 40 may be used.

In another embodiment of the invention shown in drawing FIG. 9, amulti-IC chip package 10 is shown with a stack 12 of primary packages 14as previously described. The outer leads 16 of the primary packages 14are truncated to extend only a short distance outward from the packages.The connector 36 comprises a series of buses 40 formed of a flowableconductive material which sets to a hard but flexible conductor capableof high conductance, low impedance performance. The conductive materialof the buses 40 may be a polymer e.g., epoxy, containing small particlesof conductive metal, i.e., silver, gold or aluminum. Alternatively, thebus material may be a polymer having sufficient conductance and lowimpedance for high-speed operation. Examples of conductive polymersinclude doped polyacetylene, polypyrrole, polythiophene and polyaniline.The dopant is selected to provide the desired electrical properties andmay be, for example, iodine. The material may be selected to set upon achange in temperature or by radiation, for example. If necessary,chemical agents for retarding or enhancing the setting speed may beincluded in the polymer formulation.

As shown in drawing FIG. 10, each bus 40 is formed by passing conductivepolymer 66 with a controlled setting rate in a minute stream 68 from anoutlet 74 of a polymer extruder 70. The extruder is moved up and/or downin a vertical direction 72 and in a horizontal direction 76 to join theequivalent outer leads 16 of the primary packages 14 with the conductivepads 34 of the host circuit board 30. The bus 40 is built up to thedesired cross-section for optimal device performance. A plurality, oreven all of the buses 40, may be formed simultaneously using a polymerextruder 70 with multiple outlets 74.

In the embodiments of drawing FIGS. 1-10, the multi-IC chip package isadaptable to stacks 12 of primary packages 14 having outer leads 16 onone, two, three or four sides. The stack 12 may comprise two or moreprimary packages 14, but typically will comprise about four packages,each with outer leads 16 on one or two sides.

Another embodiment of the invention is depicted in FIGS. 11 and 12. Themulti-IC chip package 80 has a stack connector 82, illustrated ascomprising a cage 84, for holding by friction an exemplary stack 86 ofeight primary packages 14. The cage 84 is shown to contact a portion orportions of lateral edge 26 of each primary package 14, and closelyapproach or contact the package ends 22, 24. The cage 84 partiallyencloses the primary packages 14 to retain them as a stack. The cage 84may be formed of a thin metal sheet, a strong polymeric material,ceramic, or the like. The cage 84 is most easily formed from a metalsheet, extruded metal, extruded plastic, molded plastic, thermoplastic,etc., typically of five (5) to one hundred (100) mils thickness 100,which is cut and bent at 90 degrees at each of the four corners 102,104, 106, and 108, forming the five panels 110, 112, 114, 116 and 118. Agap 120 between coplanar panels 116 and 118 permits easy removal ofprimary packages 14 from the cage 84. Particularly when formed of metal,the high heat conductivity of the cage 84 results in enhanced heatdissipation from the multi-IC chip package or module 80 during use. Thecage 84 also acts as a heat sink to minimize temperature variations ofthe primary packages 14.

On one interior wall 88, herein called the “active wall” of the cage 84,a thin “flex PCB” 92 is attached by a layer 94 of elastomeric adhesive.The thickness 96 of the elastomeric adhesive layer 94 is controlled toprovide a desired degree of flexibility. Buses 90 are formed on the flexPCB 92 with a pitch 48 matching the pitch 49 of the outer leads 16, andare positioned to contact the sets of corresponding outer leads 16 ofthe primary packages 14 when they are inserted into the cage 84. Thebuses 90 may be metal strips attached to the flex PCB 92 by adhesive,not shown, or may be formed by metallization and lithographic busseparation, for example. If desired, the outer leads 16 of the primarypackages 14 may be soldered to the buses 90 or connected to the buses 90using suitable conductive material.

The lower end 124 of each of the buses 90 is shown as comprising ahorizontal portion insulated from the cage 84 by non-conductive adhesivelayer 94. The lower end 124 may be attached to a conductive pad or lead34 of the host circuit board 30 by methods well-known in the art, e.g.by surface mounting with solder, bonding with conductive adhesive, andthe like.

The thin flex PCB 92 and elastomeric adhesive layer 94 provideresilience by which variations in dimensions of the primary packages 14and their buses 90 are accommodated. Typically, the thickness 98 of theflex PCB 92 is about one (1) to five (5) mils, and the thickness 96 ofthe adhesive layer is about three (3) to eight (8) mils, but thicknesseslesser or greater than these values may be used.

As shown, the outer leads 16 of the primary packages 14 are bent to flexwith compressive forces imposed by the cage 84, flex PCB 92 andelastomeric adhesive layer 94. Thus, the electrical connections aremaintained by compression and friction. The primary packages 14 may beeasily inserted and extracted merely by pulling them from the cage 84.Desoldering or other steps of heating, cutting, etc. are not required toremove a primary package 14.

Where sharp forces on the host circuit board 30 may loosen a primarypackage 14 within the cage 84, a small dab(s) of adhesive may be used tofix the topmost primary package 14 to the cage. The adhesive may beeasily removed if necessary to replace a primary package. Alternatively,a small node or nodes 122 of polymeric material may be formed on one ormore cage panels 110, 112, 114, 116 and 118 to provide an additionalresistance to removal of any primary package 14. The nodes 122 may beribs which conform to the shape of primary packages 14 to maintain theentire exemplary stack 86 immobile during use, yet allow easy removal.

In an example of this embodiment, a multi-IC chip package 80 with eighttypical primary packages 14 eight-hundred (800) mils in length andfour-hundred-fifty (450) mils in width may have an overall height ofless than about ten (10) mm. This embodiment of a multi-IC chip package80 is most aptly applied to primary packages 14 having outer leads 16along one side only. However, two opposing flex PCB members 92 withbuses 90 could be attached to opposing inner walls of a cage 84 toaccommodate primary packages 14 with outer leads 16 along both opposinglateral edges 26 and 28.

In use, the cage 84 with attached flex PCB 92 and buses 90 is attachedto the host circuit board 30 with adhesive and the bus lower ends 124are soldered or otherwise attached to the conductive pads or leads 34 ofthe host circuit board 30. The primary packages 14 are then inserted andpushed downwardly within the cage 84 to form an exemplary stack 86, theouter leads 16 of each primary package compressed slightly during theinsertion step.

The footprints of the multi-IC chip packages 10 and 80 are only slightlylarger than the footprint of a primary package 14 which is stacked inpackages 10 and 80. Thus, the density is considerably greater than theSIMM and DIMM packages currently in use. The number of primary packages14 which may be incorporated in the stack is typically eight or more,but fewer than eight may be used.

Another embodiment of the multi-IC chip package is illustrated indrawing FIG. 13. This multi-IC chip package 130 is similar to thepackage 80 of drawing FIGS. 11 and 12, except that the cage 132 has butthree full panels and has no flex PCB or buses. The cage 132 is rotatedrelative to cage 84 of package 80 so that the outer leads 16 of theprimary packages 14 may be directly attached to conductive pads 34 orelongate leads of the host circuit board 30 without an interveningpanel. The primary packages 14 have their major upper and lower surfaces18, 20 in a vertical attitude and are stacked horizontally. Thus, theheight dimension 134 is the same regardless of the number of primarypackages 14 in the stack. The two opposed cage walls are attached to thehost circuit board 30, e.g. by adhesive 136 or other means, such as snappins, not shown in drawing FIG. 13, which are fitted into holes in thehost circuit board 30. Alternately, the cage 132 may be soldered to thecircuit board 30.

Nodes 122, such as small ribs, may be incorporated into inner walls ofthe cage 132 to provide resistance to removal of the primary packages 14from the cage.

The footprint of the multi-IC chip package 130 is only slightly largerthan the footprint of a primary package 14 which is stacked in packages10 and 80. Thus, the density is considerably greater than the SIMM andDIMM packages currently in use.

The invention provides for the use of buses which are relatively shortand of enhanced cross-section to produce low impedance at high clockspeeds, i.e., up to 800 MHZ, and relatively high power ratings. Themulti-IC chip packages are easy to produce with high accuracy. Primarypackages using well-developed technologies and having pretested highreliability are used in the stacks. The invention is applicable tohigh-speed memory modules which are to supersede the SIMM and DIMMpackages.

As indicated in the foregoing, each embodiment of the multi-IC chippackage of the invention has particular advantages under particularcircumstances.

It is apparent to those skilled in the art that various changes andmodifications may be made to the multi-IC chip stacked package andpackage connector thereof in accordance with the disclosure hereinwithout departing from the spirit and scope of the invention as definedin the following claims.

1. A method for connecting a horizontally stacked plurality of primaryintegrated circuit packages on a substrate having a plurality ofcircuits thereon, each primary integrated circuit package having aplurality of outer leads and having a plurality of sides, comprising:providing a cage enclosing at least three sides of the plurality ofsides of each primary integrated circuit package of the stackedplurality of primary integrated circuit packages; and attaching the cageto the substrate using one of adhesive and snap pins fitting in holes inthe substrate, the cage connecting at least one outer lead of theplurality of outer leads of the stacked plurality of primary integratedcircuit packages to at least one conductive bus of a plurality of spacedtransverse conductive buses, with a portion of a semi-continuousflexible tape located within the cage.
 2. A method for connecting astacked plurality of integrated circuit packages on a substrate having aplurality of circuits thereon, each integrated circuit package having aplurality of outer leads and having a plurality of sides, comprising:providing a cage enclosing at least three sides of the plurality ofsides of each integrated circuit package of the stacked plurality ofintegrated circuit packages; and attaching the cage to the substrateusing one of adhesive and snap pins fitting in holes in the substrate,the cage connecting at least one outer lead of the plurality of outerleads of the stacked plurality of integrated circuit packages to atleast one conductive bus of a plurality of spaced transverse conductivebuses, with a portion of a semi-continuous flexible tape located withinthe cage.
 3. A stacking method for a plurality of integrated circuitpackages on a substrate having a plurality of circuits thereon, eachintegrated circuit package having a plurality of outer leads and havinga plurality of sides, comprising: providing a cage enclosing at leastthree sides of the plurality of sides of each integrated circuit packageof the plurality of integrated circuit packages; and attaching the cageto the substrate using one of adhesive and snap pins fitting in holes inthe substrate, the cage connecting at least one outer lead of theplurality of outer leads of the plurality of integrated circuit packagesto at least one conductive bus of a plurality of spaced transverseconductive buses, with a portion of a semi-continuous flexible tapelocated within the cage.
 4. A stacking method for integrated circuitpackages on a substrate having a plurality of circuits thereon, eachintegrated circuit package having a plurality of outer leads and havinga plurality of sides, comprising: providing a cage enclosing at leastthree sides of the plurality of sides of each integrated circuit packageof the integrated circuit packages; and attaching the cage to thesubstrate using one of adhesive and snap pins fitting in holes in thesubstrate, the cage connecting at least one outer lead of the pluralityof outer leads of the integrated circuit packages to at least oneconductive bus of a plurality of spaced transverse conductive buses,with a portion of a semi-continuous flexible tape located within thecage.
 5. An assembly method for integrated circuit packages on asubstrate having a plurality of circuits thereon, each integratedcircuit package having a plurality of outer leads and having a pluralityof sides, comprising: forming a cage for enclosing at least three sidesof the plurality of sides of each integrated circuit package of theintegrated circuit packages; and attaching the cage to the substrateusing one of adhesive and snap pins fitting in holes in the substrate,the cage connecting at least one outer lead of the plurality of outerleads of the integrated circuit packages to at least one conductive busof a plurality of spaced transverse conductive buses, with a portion ofa semi-continuous flexible tape located within the cage.
 6. An assemblymethod for integrated circuit packages on a substrate having a pluralityof circuits thereon using a cage, each integrated circuit package havinga plurality of outer leads and having a plurality of sides, comprising:enclosing at least three sides of the plurality of sides of eachintegrated circuit package of the integrated circuit packages using thecage; and attaching the cage to the substrate using one of adhesive andsnap pins fitting in holes in the substrate, the cage connecting atleast one outer lead of the plurality of outer leads of the integratedcircuit packages to at least one conductive bus of a plurality of spacedtransverse conductive buses, with a portion of a semi-continuousflexible tape located within the cage.
 7. A method for connecting ahorizontally stacked plurality of primary integrated circuit packages ona substrate having a plurality of circuits thereon using a cage, eachprimary integrated circuit package having a plurality of outer leads andhaving a plurality of sides, comprising: enclosing at least three sidesof the plurality of sides of each primary integrated circuit package ofthe stacked plurality of primary integrated circuit packages using thecage; and attaching the cage to the substrate using one of adhesive andsnap pins fitting in holes in the substrate, the cage connecting atleast one outer lead of the plurality of outer leads of the stackedplurality of primary integrated circuit packages to at least oneconductive bus of a plurality of spaced transverse conductive buses,with a portion of a semi-continuous flexible tape located within thecage.
 8. A method for connecting a stacked plurality of integratedcircuit packages on a substrate having a plurality of circuits thereonusing a cage, each integrated circuit package having a plurality ofouter leads and having a plurality of sides, comprising: enclosing atleast three sides of the plurality of sides of each integrated circuitpackage of the stacked plurality of integrated circuit packages usingthe cage; and attaching the cage to the substrate using one of adhesiveand snap pins fitting in holes in the substrate, the cage connecting atleast one outer lead of the plurality of outer leads of the stackedplurality of integrated circuit packages to at least one conductive busof a plurality of spaced transverse conductive buses, with a portion ofa semi-continuous flexible tape located within the cage.
 9. A stackingmethod for a plurality of integrated circuit packages on a substratehaving a plurality of circuits thereon using a cage, each integratedcircuit package having a plurality of outer leads and having a pluralityof sides, comprising: enclosing at least three sides of the plurality ofsides of each integrated circuit package of the plurality of integratedcircuit packages using the cage; and attaching the cage to the substrateusing one of adhesive and snap pins fitting in holes in the substrate,the cage connecting at least one outer lead of the plurality of outerleads of the plurality of integrated circuit packages to at least oneconductive bus of a plurality of spaced transverse conductive buses,with a portion of a semi-continuous flexible tape located within thecage.
 10. A stacking method for integrated circuit packages on asubstrate having a plurality of circuits thereon using a cage, eachintegrated circuit package having a plurality of outer leads and havinga plurality of sides, comprising: enclosing at least three sides of theplurality of sides of each integrated circuit package of the integratedcircuit packages using the cage; and attaching the cage to the substrateusing one of adhesive and snap pins fitting in holes in the substrate,the cage connecting at least one outer lead of the plurality of outerleads of the integrated circuit packages to at least one conductive busof a plurality of spaced transverse conductive buses, with a portion ofa semi-continuous flexible tape located within the cage.
 11. An assemblymethod for integrated circuit packages on a substrate having a pluralityof circuits thereon using a cage, each integrated circuit package havinga plurality of outer leads and having a plurality of sides, comprising:enclosing at least three sides of the plurality of sides of eachintegrated circuit package of the integrated circuit packages in thecage; and attaching the cage to the substrate using one of adhesive andsnap pins fitting in holes in the substrate, the cage connecting atleast one outer lead of the plurality of outer leads of the integratedcircuit packages to at least one conductive bus of a plurality of spacedtransverse conductive buses, with a portion of a semi-continuousflexible tape located within the cage.